The present invention relates to methods for making thin film transistors (TFTs), and more particularly to methods for making TFTs of a type having a bottom gate.
Generally, TFTs are widely used in static random access memories (SRAMs) or in livid crystal displays (LCDs) as a load device instead of a load resistor.
Modern technology produces mega-bit-sized static random access memories with reduced cell size and low supply voltage (Vcc), and thus such SRAMs use polysilicon TFTs as loads instead of polysilicon resistors in order to obtain high charging current and low leakage current for the SRAM cell. Therefore it is desirable for the TFT to have high on current and low off current. However, the ratio of on/off current of polysilicon TFTs typically is not high enough to satisfy cell operation stability, which is lowered due to the cell size reduction and lowering of the power supply voltage. If cell size is decreasing, then off current is increasing due to short channel effects, but on current is not increasing, and thus the ratio of on/off current is lowered.
An attempt that has been made to solve this problem for megabit SRAMs is disclosed in the paper "16 Mbit SRAM Cell Technologies for 2.0 V Operation" by H. Ohkubo et al., Technical Digest IEDM 1991, pages 481 to 483. In this paper, the key features of the disclosed technologies include: 1) a symmetrical cell configuration; 2) an access transistor with an N- offset resistor; 3) a ground plate expanded on the cell area; and 4) a polysilicon TFT with an LDO (Lightly Doped Offset) structure, all of which utilize a Self Aligned Contact (SAC) process. The symmetrical cell configuration, the ground plate and the TFT with the LDO structure contribute to cell operation stability.
A conventional process for fabricating a polysilicon TFT of a bottom gate type with an LDO structure is depicted in FIG. 1.
As shown in FIG. 1A, insulating layer 12 is deposited on surface 11 where a TFT is to be formed, and a polysilicon layer is deposited on insulating layer 12. The polysilicon layer is etched to form gate electrode (gate line) 13 by a photolithography process. After this step, gate insulating layer (gate insulator) 14 is formed on gate electrode 13 and insulating layer 12 by a high temperature oxide deposition process. Body polysilicon 15 (or amorphous silicon) is deposited on gate insulator 14 and silicon ions are implanted in order to improve the electrical characteristics. Then, amorphous body silicon layer 15 is annealed for 5 hrs and more at 600.degree.+/-50.degree. C. After this, as illustrated implantation process 16 may be carried out for purposes of regulating the threshold voltage.
In the next step, as shown in FIG. 1B, the low concentration impurity region, LDO drain junction 19, is formed at one side of gate line in body polysilicon 15 by N.sup.- impurity ion implantation 18 with photoresist mask 17 serving to limit the drain zone for the Lightly Doped Drain (LDD) structure.
Next, as shown in FIG. 1C, highly doped drain and source regions are formed by implantation of N.sup.+ impurity ions 110 after patterning photoresist pattern 17' for protecting the LDD junction against the implantation using an offset S/D photoresist mask.
With this type of TFT, since body polysilicon layer 15 is formed on gate 13 and of an angular structural shape, a considerable amount of leakage current still occurs, and due to the gate electrode the step coverage is poor. Therefore, the on/off current ratio is still low, and a subsequent metallization process is not easy.